library ieee;
use ieee.std_logic_1164.all;
use work.mis_componentes.all;


entity sum4bits is
port(a:in std_logic_vector(3 downto 0);
	 b:in std_logic_vector(3 downto 0);
	 s:out std_logic_vector(3 downto 0);
	 Cout:out std_logic);
end sum4bits;

architecture sum4 of sum4bits is
signal temp:std_logic_vector(3 downto 0);
begin

U1:sum1bit PORT MAP(a=>a(0),b=>b(0),Cin=>'0',s=>s(0),Cout=>temp(0));
U2:sum1bit PORT MAP(a=>a(1),b=>b(1),Cin=>temp(0),s=>s(1),Cout=>temp(1));
U3:sum1bit PORT MAP(a=>a(2),b=>b(2),Cin=>temp(1),s=>s(2),Cout=>temp(2));
U4:sum1bit PORT MAP(a=>a(3),b=>b(3),Cin=>temp(2),s=>s(3),Cout=>temp(3));

cout<=temp(3);
end sum4;